@Rhythm.
Just thought I'd let you know that I've now done the first chapter and project of the book. So that means I've implemented fifteen chips in HDL (and tested them successfully in the hardware simulator), using only Nand or any gates I'd previously completed, as per the rules of the project. This is the order I did them in and in brackets are the distinct type of gates used in each, and in square brackets the total number or each gate used:
Not(Nand[1]), And(Nand[3]), Or(Not[2], Nand[1]), Xor(Not[1], And[2], Or[1]), Mux(Not[3], And[5], Or[2]), DMux(Not[1], And[2]), Not16(Not[16]), And16(And[16]), Or16(Or[16]), Mux16(Mux[16]), Or8Way(Or[7]), DMux4Way(DMux[3]), DMux8Way(DMux[1], DMux4Way[2]), Mux4Way16(Mux16[3]), Mux8Way16(Mux16[1], Mux4Way16[2])
The reason I put all that up there is because there's no course on at the moment, just the textbook, so no feedback of any kind to let me know if I'm on the right track. I know in a sense it doesn't matter how each gate is implemented... if it works it works and since they're encapsulated like classes in programming I can work on them any time... but I still want them to be as optimised as possible. I was hoping you could give it an expert glance and let me know if any chips use way too many gates or the wrong types? And just as an aside, doing that showed that it was indeed all made out of Nand... so now I fully understand what you mean by a universal gate
I'm pretty happy with most of them but not my mux... my mux sucks
I couldn't figure out how to do this one so I worked out the 'canonical minterm representation' from the truth table as f(x,y,sel)=xys+xys+xys+xys. (Using underlines here to represent Not). And then reduced it intuitively to xys+xys+xy. Then just modelled that cumbersome circuit in HDL, but I'm hoping that canonical representation can be simplified even further but I don't know how to do it. I looked online and there is one way, involving a colourful square, which I can't remember the name of, and human pattern matching abilities, but I don't think I'm ready for that yet... though it looks like it is something I will enjoy doing at some point, and was hoping there might be a simpler, more procedural method, just to get it down a little bit more, if not all the way?
Anyway, you were so right... it's so addictive I've thought of nothing else for the last few days... getting straight to work as soon as I woke up and all day long until I went to bed... and then... like you... finding myself dreaming about it (never thought I'd find myself dreaming about demuxers... or even knowing what they were ). And I've got my dad interested as well and have bought him a copy of the book (not yet delivered)... so we can learn together, bounce ideas off each other, compare our circuits etc, and get involved in a bit of friendly competition It's been hard... so many times thinking 'I wish I had the gate I'm currently building' ...so the challenge is constant with each and every gate, but great fun... the ultimate type of puzzle: one where you learn something and achieve something by solving it. I can really see myself getting into this big time, and I already feel like I've learnt so much just from working on this first chapter. So thank you for introducing me to it
Just thought I'd let you know that I've now done the first chapter and project of the book. So that means I've implemented fifteen chips in HDL (and tested them successfully in the hardware simulator), using only Nand or any gates I'd previously completed, as per the rules of the project. This is the order I did them in and in brackets are the distinct type of gates used in each, and in square brackets the total number or each gate used:
Not(Nand[1]), And(Nand[3]), Or(Not[2], Nand[1]), Xor(Not[1], And[2], Or[1]), Mux(Not[3], And[5], Or[2]), DMux(Not[1], And[2]), Not16(Not[16]), And16(And[16]), Or16(Or[16]), Mux16(Mux[16]), Or8Way(Or[7]), DMux4Way(DMux[3]), DMux8Way(DMux[1], DMux4Way[2]), Mux4Way16(Mux16[3]), Mux8Way16(Mux16[1], Mux4Way16[2])
The reason I put all that up there is because there's no course on at the moment, just the textbook, so no feedback of any kind to let me know if I'm on the right track. I know in a sense it doesn't matter how each gate is implemented... if it works it works and since they're encapsulated like classes in programming I can work on them any time... but I still want them to be as optimised as possible. I was hoping you could give it an expert glance and let me know if any chips use way too many gates or the wrong types? And just as an aside, doing that showed that it was indeed all made out of Nand... so now I fully understand what you mean by a universal gate
I'm pretty happy with most of them but not my mux... my mux sucks
I couldn't figure out how to do this one so I worked out the 'canonical minterm representation' from the truth table as f(x,y,sel)=xys+xys+xys+xys. (Using underlines here to represent Not). And then reduced it intuitively to xys+xys+xy. Then just modelled that cumbersome circuit in HDL, but I'm hoping that canonical representation can be simplified even further but I don't know how to do it. I looked online and there is one way, involving a colourful square, which I can't remember the name of, and human pattern matching abilities, but I don't think I'm ready for that yet... though it looks like it is something I will enjoy doing at some point, and was hoping there might be a simpler, more procedural method, just to get it down a little bit more, if not all the way?Anyway, you were so right... it's so addictive
I've thought of nothing else for the last few days... getting straight to work as soon as I woke up and all day long until I went to bed... and then... like you... finding myself dreaming about it (never thought I'd find myself dreaming about demuxers... or even knowing what they were ). And I've got my dad interested as well and have bought him a copy of the book (not yet delivered)... so we can learn together, bounce ideas off each other, compare our circuits etc, and get involved in a bit of friendly competition It's been hard... so many times thinking 'I wish I had the gate I'm currently building' ...so the challenge is constant with each and every gate, but great fun... the ultimate type of puzzle: one where you learn something and achieve something by solving it. I can really see myself getting into this big time, and I already feel like I've learnt so much just from working on this first chapter. So thank you for introducing me to it
